1. Field of the Invention
The present invention relates to a method for manufacturing a mask ROM and, more particularly, to a method for manufacturing a mask ROM of a flat cell structure.
2. Description of the Related Art
A mask ROM is one of non-volatile devices, which stores necessary information by using mask process. The mask process for may be carried out in device isolation process or metal wiring process, by ion implantation to channel region of memory cell. The ion implantation process generates the threshold voltage difference between ion-implanted cells and the others, thereby determining stored data.
Generally, the mask ROM has a flat cell structure to improve operation speed by increasing cell currents, as shown in FIG. 1.
FIG. 1 is a schematic plan of mask ROM having a conventional flat cell structure, wherein a reference code A is a flat cell array region, B is a peripheral circuit region, 10 is an active region, and 20 is a code mask region.
As shown in the drawing, a plurality of BN+ (Buried N+) diffusion layers 12 and word lines 14 are cross-arranged with a predetermined distance in a row direction and a column direction, respectively, on a flat cell array region A. On a peripheral region B, a BN+ diffusion layer 12 is provided and a bit line contact 16 is formed to be in contact with the diffusion layer 12. Here, the BN+ diffusion layer 12 is employed as junctions for bit line and source/drain regions of cell transistor. The word line 14 has the same width as the channel width in memory cell.
According to the mask ROM of flat cell structure thus constructed, in the memory cell array region, isolation of cells is conducted not with a device isolation layer formed by LOCOS or STI process but by a device isolation layer covering a whole memory cell array region. And, source/drain regions of cell transistor are not separated since they comprise BN+ diffusion layers 12, thereby the contact of BN+ diffusion layer 12 is arranged on the peripheral circuit region, not on the memory cell array region.
Therefore, the mask ROM having a flat cell structure can accomplish high integration without contact with a device isolation layer in the memory cell array region.
FIG. 2 is a flow chart showing a method for manufacturing a mask ROM of a flat cell structure according to a conventional art.
As shown in the drawing, a device isolation layer is formed on a semiconductor substrate by a device isolation process S1. A well is formed on the substrate by an ion implantation process for the well formation S2. It is possible to perform the well process S2 prior to the device isolation process S1. A BN+ diffusion layer is formed on the substrate by a BN+ ion implantation process S3. A gate oxide layer and a gate electrode are formed on the substrate by a thermal oxidation process S4 and a conductive layer deposition and etching process 5. A cell isolation is performed by ion implantation process S6. Source/drain is formed by a high concentration ion implantation process S7.
Although it is not shown in the drawings, data coding is performed in accordance with ion implantation process using a mask.
FIGS. 3A to 3F are sectional views showing a method for manufacturing a mask ROM of flat cell structure according to a conventional art. The drawing on the left is a sectional view of flat cell array region (A) and one on the right is a sectional view of peripheral circuit region (B).
Referring to FIG. 3A, a first insulating layer 31a, a buffer layer 31b and a second insulating layer 31c are sequentially formed on a semiconductor substrate 30. The first and the second insulating layers 31a, 31c comprise oxide layers and the buffer layer 31b comprises a nitride layer. A first sensitive film 32 is applied on a multi-layered film 31 comprising a laminated layer of the first insulating layer 31a, the buffer layer 31b and the second insulating layer 31c and then, the first sensitive film 32 is exposed and developed to expose the multi-layered film of trench formation region on the peripheral circuit region (B).
Referring to FIG. 3B, the multi-layered film 31 of the exposed peripheral circuit region (B) is etched by using the patterned first sensitive layer 32 as an etching barrier, thereby exposing the substrate corresponding to the trench formation region of peripheral circuit region (B) . A trench 33 is formed by etching the exposed substrate to a predetermined depth.
Referring to FIG. 3C, the first sensitive film is removed. A linear oxide layer 34 is formed on the multi-layered film 31 of flat cell array region (A) and the trench 33 and the multi-layered film 31 of the peripheral circuit region (B) in accordance with a thermal oxidation process. An oxide layer 35 is formed on the linear oxide layer 34 to fill up the trench 33.
Referring to FIG. 3D, the oxide layer is polished to expose the surface of second insulating layer of the multi-layered film in accordance with a CMP (Chemical Mechanical Polishing) process, thereby forming a device isolation layer 35a in a trench type on the peripheral circuit region (B). The second insulating layer and the buffer layer of the multi-layered film are removed.
Referring to FIG. 3E, a third insulating layer 36 is formed on the entire surface of semiconductor substrate 30. A second sensitive film 37 is applied on the third insulating layer and then, exposed and developed to expose the third insulating layer corresponding to BN+ diffusion layer formation region of flat cell array region (A).
Referring to FIG. 3F, the exposed third insulating layer of flat cell array region (A) and the first insulating layer thereunder are etched by using the patterned second sensitive film as an etching barrier, thereby exposing the BN+ diffusion layer formation region of substrate. The second sensitive film is removed. A predetermined conductive impurities are ion-implanted to form a BN+ diffusion layer, thereby forming a BN+ ion implantation region 38 on the surface of the exposed flat cell array region (A). The BN+ ion implantation is conducted by conductive impurities opposite to the substrate, for example, n-type impurities such as P or As in a p-type substrate.
Referring to FIG. 3G, the resulting structure is subjected to annealing process, thereby forming a BN+ diffusion layer 38a by activating ion impurities implanted in the substrate. At the same time, a barrier oxide layer 39 is formed on the surface of the BN+ diffusion layer 38a. The barrier oxide layer 39 is grown to have a thickness sufficient to prevent damage of BN+ diffusion layer 38a and increase of parasitic capacitance between the gate electrode and junctions in a later step. The third insulating layer and the first insulating layer are removed from the flat cell array region (A) and the peripheral circuit region (B), thereby providing a BN+ diffusion layer 38a and a barrier oxide layer 39 on the substrate of flat cell array region (A), and a trench type isolation layer 35a on the substrate of the peripheral circuit region (B).
Although it is not shown in the drawings, a LOGIC process including a gate process is performed on the resulting substrate having the BN+ diffusion layer 38a and the device isolation layer 35a, thereby completing a mask ROM of a flat cell structure.
However, the conventional method has several problems in LOGIC process less than 0.25 μm.
First, it is not needed to perform device isolation of memory cells in a mask ROM of flat cell structure, thereby the whole cell region is active region. Therefore, device isolation process by STI is performed only on the peripheral circuit region and the STI process includes trench fill up of oxide layer and CMP process of the oxide layer. However, there arise problems in that the active region of flat cell array region is larger than that of peripheral circuit region, thereby the oxide layer is underpolished on the flat cell array region and on the peripheral circuit region, the oxide layer is overpolished during the CMP process.
It is possible to overcome the CMP problem by adding a dummy oxide layer pattern on the large active region or adding a mask and etching process to remove the underpolished oxide layer. However, there arises another problem that the degree of integration is lowered due to the added dummy oxide layer pattern and manufacturing time and cost are increased by the additional steps.
Finally, device isolation and BN+ diffusion layer formation are carried out respectively, thereby increasing the number of unit processes to LOGIC process and manufacturing time and cost are also increased.